1. Field of the Invention
The present invention relates in general to a signal processing circuit, such as an image sensor, for processing an analog signal. In addition, the invention relates to a linear image sensor and an area image sensor each of which is loaded with the signal processing circuit. Also, the invention relates to a close contact type image sensor having a plurality of linear image sensor ICs mounted thereto.
2. Related Background Art
A circuit diagram of an image sensor of Related Art Example 1 is shown in FIG. 19, and a timing chart of the image sensor of Related Art Example 1 is shown in FIG. 20 (refer to JP 11-112015 A (page 4 and page 5, and FIG. 1) for example).
Related Art example 1 aims at providing a high performance close contact type image sensor which requires no dark correction through removal of an FPN (Fixed Pattern Noise) due to a difference in level among chips.
In accordance with Related Art Example 1, there is provided a close contact type image sensor constituted by a semiconductor device including on the same semiconductor substrate: a sensor module in which a plurality of semiconductor optical chips are mounted on a mounting substrate and each have signal hold circuit for reading out and holding optical signals and noise signals of a plurality of photoelectric converter, common output lines through which the optical signals and the noise signals of the signal hold circuit are outputted, respectively, reset means for resetting the common output lines, respectively, and read means for reading out and outputting the optical signals and the noise signals from the common output lines, respectively; optical signal input buffer means for receiving as its input the noise signals and the optical signals of the sensor chips in the sensor module; differential means for taking a difference between a signal of a noise signal input buffer amplifier and a signal of an optical signal input buffer amplifier; and voltage clamp means for clamping an output signal of the differential means. The close contact type image sensor is characterized in that the voltage clamp means clamps a state in which the optical signal common output lines and the noise signal common output lines are reset.
In addition, an amplifier chip 200 and a sensor chip 100 are constructed using different chips.
In addition, a circuit diagram of an image sensor IC of Related Art Example 2 is shown in FIG. 21, and a timing chart of the image sensor IC of Related Art Example 2 is shown in FIG. 22 (refer to JP 11-239245 A (page 3 and page 4, and FIG. 1) for example).
An N-type region of a photodiode 101 is connected to a positive power supply voltage terminal VDD, and a P-type region of the photodiode 101 is connected to a drain of a reset switch 102 and a gate of a source follower amplifier 103. A reference voltage VREF1 is applied to a source of the reset switch 102. A source as an output terminal of the source follower amplifier 103 is connected to a read switch 105 and a constant current source 104. A constant voltage as a reference voltage VREFA is applied to a gate of the constant current source 104. The number of sets of constituent elements provided within a frame of a photoelectric conversion block An shown in FIG. 8 is identical to the number of pixels, and a read switch 105 of each block is connected to a common signal line 106. Note that the photoelectric conversion block An shows a photoelectric conversion block of an n-th bit.
The common signal line 106 is connected to an inverting input terminal of an operational amplifier 109 through a resistor 110. An output terminal of the operational amplifier 109 is connected to an output terminal 116 through a chip selection switch 112 and a capacitor 113. The common signal line 106 is connected to a signal line reset switch 107, and a reference voltage VREF2 is applied to a source of the signal line reset switch 107. A resistor 111 is connected between an output terminal and the inverting input terminal of the operational amplifier 109, and a voltage appearing at a non-inverting input terminal of the operational amplifier 109 is fixed to a constant voltage VREF3. The operational amplifier 109, the resistor 110, and the resistor 111 constitute an inversion amplifier D.
The output terminal 116 of the image sensor is connected to a drain of a MOS transistor 114, and a reference voltage VREF4 is applied to a source of the MOS transistor 114. In addition, a capacitor 115 including a parasitic capacity or the like is also connected to the output terminal 116 of the image sensor. The capacitor 113, the capacitor 115 and the MOS transistor 114 constitute a voltage clamp circuit C.
However, the image sensor of Related Art Example 1 has a disadvantage that the amplifier chip 200 and the sensor chip 100 need to be provided separately from each other, thereby increasing the number of constituent elements. That is, while the amplifier chip serves to amplify a difference between the reference signal and the optical signal, if amplifiers 201, 202, and 203 are self-contained in the sensor chips, a difference in offset appears among these sensor chips because of offset of the amplifiers 201, 202, and 203, which raises a problem. In addition, there arises a problem in that the circuit of the amplifier chip cannot cope with a sensor chip of such a type as to be adapted to output the reference signal and the optical signal to the same common signal line in order. Moreover, there also arises a problem in that if the image sensor is provided with an amplification function, then an offset of the amplifier is also amplified.
In addition, the image sensor of Related Art Example 2 has a problem in that if a difference between the voltage of VREF3 and the voltage appearing at the terminal 106 is large, then a level of the output signal of the inversion amplifier D is easy to be beyond an output range. That is, the difference between the voltage of VREF3 and the voltage appearing at the terminal 106 is amplified at a magnification factor of a gain of the inversion amplifier D. Thus, if the gain of the inversion amplifier D is large, then a level of the output signal of the inversion amplifier D becomes beyond the output range. In addition, while the offset of the source follower circuit 103 fluctuates every bit, the voltage of VREF3 is constant. Thus, it is difficult to ensure a linear area having broad photoelectric conversion characteristics for outputs of all bits.
Also, in the image sensor of Related Art Example 2, after the optical signal is read out after storage of photocharges, the photodiode is reset, and the reference signal is then read out to take a difference between the optical signal and the reference signal. For this reason, a reset noise contained in the reference signal is different from that contained in the optical signal. That is, there arises a problem in that since the different reset noises of the timings are compared with each other, a random noise becomes large. In particular, the reset voltage VREF1 is normally supplied from a reference voltage circuit provided inside a corresponding one of the image sensor ICs. For this reason, thermal noises are contained in the reset voltage. Normally, the thermal noises can be reduced by a capacitor having a large capacity connected to a reference voltage terminal. However, practically, since a capacitor having a large capacity cannot be provided inside an IC, it is difficult to reduce these thermal noises. For this reason, whenever the reset is carried out, a reset level of the photodiode fluctuates. Consequently, there arises a problem in that a signal level is changed every read line, and hence streaks are formed in a read-out image. In addition, there also arises a problem in that since the reset voltages of the image sensor ICs are different from one another and hence a reverse bias voltage of the photodiode differs every IC, a sensitivity varies among ICs.